This invention relates generally to phase-change memory, and more particularly to methods and apparatus for programming multilevel phase-change memory cells.
Phase change memory (PCM) is a non-volatile solid-state memory technology that exploits the reversible, thermally-assisted switching of specific chalcogenide compounds, such as GST, between states of different electrical conductivity. PCM is considered a candidate technology for flash memory replacement and storage-class memory. Besides many attractive features such as low read and write latency, high endurance, long retention and excellent scalability, PCM offers multibit operation which is a key factor for increasing capacity and reducing cost in memory technologies. Multibit, or multilevel, storage is usually achieved by means of an iterative write-and-verify (WAV) scheme, which aims to compensate for the variability in cell programming characteristics typically observed in large memory arrays.
When writing to multilevel PCM, each PCM cell can be set to any one of s>2 different states, or levels, which exhibit different electrical characteristics. The s programmable cell states defined for multilevel operation correspond to different ratios of amorphous and crystalline phases in the chalcogenide material. These, in turn, correspond to different values of a cell state metric, typically electrical resistance, which is measured to detect cell state on read back. To program a PCM cell to a particular cell state, a programming pulse is applied to the cell to heat the chalcogenide material and induce the desired cell state on cooling. The programming pulses can be produced by applying appropriate control signals in the PCM circuitry. For example, a voltage pulse can be applied to a cell by applying a bias voltage signal at a bit-line (BL) of a memory cell array (voltage-mode programming). A particular cell may be addressed via a combination of the BL signal and a further control signal applied to an access device in a word-line (WL) of the array. Depending on the nature of such an access device, a signal pulse applied to the access device may also be used to produce a programming pulse for the cell. For instance, an FET connected to the cell can be used as a voltage-controlled current source such that a voltage pulse applied via the word-line to the gate of the FET produces a programming current pulse in the cell (current-mode programming).
There exist different methods of programming a PCM cell by changing different attributes of the programming pulse, specifically by changing the pulse amplitude, or the pulse duration, or the duration of the trailing edge of the pulse. These different programming methods are discussed in: “Multi-level Phase-Change Memory Modeling and Experimental Characterization”, Pantazi et al., EPCOS 2009; and “Write strategies for 2 and 4-bit Multi-level Phase-Change Memory”, Nirschl et al., IEDM 2007. In each case, as the particular pulse attribute is varied, there is a change in the size of the amorphous region and hence a change in the associated electrical resistance of the cell. The resulting resistance vs. pulse attribute function is typically referred to as a “programming trajectory”, or “programming curve”. The programming trajectory defines the available space for level allocation in multilevel programming, i.e., for the different programmable cell states defined for multilevel operation.
A single programming pulse may be employed in a programming operation with the variable attribute of the programming pulse set appropriately to induce the desired cell state. With the iterative (WAV) technique more usually employed for multilevel PCM, a sequence of programming pulses is employed. The cell state is detected (e.g., by measuring cell-resistance) after each pulse in the sequence. The variable pulse attribute is then adjusted appropriately for the next pulse in the sequence based on the actual, measured cell state and the desired, target cell state. In this way, the process effectively progresses along the programming trajectory, gradually converging on the target cell state.
A programming technique which uses multiple programming trajectories is described in our International Patent Application publication no. WO 2011/121491 A1, and “Programming Algorithms for Multilevel Phase-Change Memory”, Papandreou et al., ISCAS 2011. With this technique, a plurality of programming trajectories is available corresponding to respective, different values of the gate voltage VG applied to a FET access device in the cell word-line. For a given value of VG, the amplitude of a bias voltage pulse at the cell bit-line is then variable to access cell states in the corresponding programming trajectory. Multiple trajectories are thus implemented here by joint control of the bit-line and word-line signals, these two signals effectively providing two knobs for programming control.